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Lots of problem solving in October. Lots of time wasted as well. I lost myself in trying to make the LPC (SuperIO) chip work properly with the FPGA (Vicky) and at first I thought it was simply timing problems with the FPGA then it occurred to me that maybe there was a underlying problem that was getting the FPGA to behave the way it was... Actually, the problem was never the FPGA, in fact there was a problem with the CPU itself that was exacerbated by the PLL clock generator on the board. Apparently the CPU is generating a lot of noise and since there is only one VCC and one GND on the chip and with a poorly decoupled power rail for it, I got into a lot of problems...
Anyway, during the month, I managed to make different part of the system work, like the CIA/RTC/SID etc...
Now, the time for Revision B has come...
More info soon!
Cheers
Stefany